1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having both analog circuits and digital circuits mounted on the same substrate, and in particular relates to a semiconductor integrated circuit adapted for a current leak test.
2. Description of the Related Art
An analog circuit such as a comparator is generally constructed including a constant-current source, and consequently, a semiconductor integrated circuit including both digital circuits and this type of analog circuits requires an extremely large current of up to several tens or several hundred times the current required by an ordinary semiconductor integrated circuit having only digital logic. This type of semiconductor integrated circuit having both analog circuits and digital circuits mounted on the same substrate will hereinafter be referred to as an analog-digital IC.
In an analog-digital IC, the inherently large drive current complicates the detection of a current leak caused by an abnormality in internal logic. Accordingly, in analog-digital ICs of the prior art, a method has been employed in which a disable circuit is provided that disables the analog circuit and cuts off circuit current and, when performing a test, a test mode signal St is activated to operate the disable circuit and cut off the current of the analog circuit.
FIG. 1(a) shows an example of an analog-digital IC provided with a conventional comparator having a disable circuit, and FIG. 1(b) is a circuit diagram of a comparator having a disable circuit. A comparator having a disable circuit will hereinafter be referred to as a D-comparator, and the intrinsic comparator portion will be referred to as the comparator.
In FIG. 1(a), reference voltage VG1 is applied to the inverting input of the D-comparator 1 and input signal Si is supplied to non-inverting input by way of input terminal Ti. Test mode signal St and inverted test mode signal StR are inputted into the input terminals TE and TER, respectively, of the D-comparator 1. When test mode signal St is active (logic 1), the operation of the comparator, i.e., the comparator portion within the D-comparator, is disabled, and when test mode signal St is inactive (logic 0), the comparator performs normal operation. In the state in which the operation of the comparator is disabled, i.e., in the disable state, the circuit current of the comparator is cut off and the output signal S1 set to high level (H level).
As shown in FIG. 1(b), the D-comparator 1 is composed of a comparator 10 made up of a differential circuit 1a and a driving circuit 1b and a disable circuit. The differential amplifier circuit 1a is an ordinary differential amplifier circuit composed of a source coupled PMOS difference transistors Qp4 and Qp5, and a current source made up of a PMOST (a PMOS transistor) Qp1, and NMOS load transistor Qn2 and Qn3. The current output of current source transistor Qpl is controlled by gate bias VG2. In the circuit shown in the figure, of the differential transistors Qp4 and Qp5, transistor Qp4 is an inverting input transistor to which reference voltage VG1 is applied. The load transistor Qn2 has a gate and drain interconnected to form a diode connection, and the signal produced at the output terminal T1 of transistor Qp4 is applied to the gate of load transistor Qn3 of non-inverted input transistor Qp5. By means of this connection, the single-ended output of the differential amplifier circuit 1a is generated at the output terminal T2 of transistor Qp5.
The drive circuit 1b is an NMOS inverter provided for driving the internal circuit 7 by supplying the output of the differential amplifier circuit 1a. The gate of load transistor Qp2 is connected to gate bias VG2.
The disable circuit is provided with NMOST Qn1 and Qn4 and PMOST Qp3. NMOST Qn1 and Qn4 are each connected in parallel to load transistors Qn2 and Qn3, and the gates of transistors Qn1 and Qn4 are connected to test mode signal St. PMOST Qp3 is connected in parallel to transistor Qp2 of the drive circuit 1b, and its gate is connected to inverted test mode signal StR. Further, when test mode signal St is active, gate bias VG2 is made a value for cutting off the drain current of transistors Qp1 and Qp2.
The circuit of FIG. 1(b) operates as follows: In normal operating mode, the test mode signal is set at low level. In this case, NMOST Qn1 and Qn4 are turned off and PMOST Qp3 is also turned off by inverted test mode signal StR of high level. As a result, the comparator performs normal operation.
In test mode, the test mode signal is set to high level. In this case, transistors Qn1 and Qn4 are turned on, thereby lowering the source-drain voltages of transistors Qn2 and Qn3. As a result, the gate voltage of transistor Qn5 becomes low-level, whereby transistor Qn5 is turned off. On the other hand, PMOS Qp3 is turned on by low-level inverted test mode signal StR, and as a result, the output S1 of the D-comparator becomes high level. At this time, the absolute value of the gate bias of transistors Qp1 and Qp2 is lowered below a threshold voltage by means of a circuit not illustrated in the figure, thereby cutting off the drain current of transistors Qp1 and Qp2.
In this way, the current of the differential amplifier circuit la and the drive circuit 1b is cut off, and moreover, the output S1 of the D-comparator 1 is fixed at a high level regardless of input signal Si.
During the test mode of the above-described analog-digital IC of the prior art, regardless of the signal supplied at the input terminal, the signal will not be transmitted to the internal circuit because the operation of the comparator is halted and its output voltage is fixed, and the internal circuit will therefore be fixed unchanged at a constant state. Consequently, there exists the problem that, in a case in which a current leak is generated in an internal state other than that fixed state, the current leak will not be detectable. In addition, there exists the problem that the failure points causing the leak cannot be analyzed.